Provide PDF Format
JEDEC JESD 35-A
- PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS
- standard by JEDEC Solid State Technology Association, 03/01/2010
- Publisher: JEDEC
$44.00$87.00
The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown.
Related Products
JEDEC JESD51-11
TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT..
$30.00 $59.00
JEDEC JESD82-6A
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM ..
$30.00 $59.00
JEDEC JESD51-6
INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR)..
$24.00 $48.00
